English
How to verify SoCs
Deepak Mahajan and Gurinder Singh Baghria, Freescale Semiconductor, India Pvt Ltd
EDN (August 24, 2012)
Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Intel co-founder Gordon Moore. Moore stated that the number of transistors on integrated circuits doubles approximately every two years. The chip makers want to pack as many functions as possible in their SoCs and provide as many feature additions to gain market share. The additional features increase the complexity and effort for verification.
A study [1] suggests that the key industry trends in the global chip design market are the escalating cost of chip design, increasing design complexity, and shorter market time for new products. The worst thing that could happen to a chipset company is a respin due to a functional bug in the product. This calls for greater concerted effort to verify complex designs in minimal time and a particular need for skilled and smart verification resources to reduce development costs. This article covers the minimum scope and some guidelines for efficient verification methodology for today’s SoCs.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology