Performance is marred by memory
Brian Bailey, EDN
August 30, 2012
For many years the industry created faster and faster processors. This was possible because more transistors were available in each technology node that could be used to produce even more complex and optimized pipelines. At the same time, voltages dropped enabling the processors to keep a lid on power consumption, a problem that if left unattended would have resulted in thermal breakdowns in the devices. But this came to a screeching halt a few years back. Physics started to work against us and while additional transistors were available, that were having diminishing impact on performance. At the same time, leakage power started to rise, meaning that power consumption was increasing, and not easy to turn unused parts off when deeply embedded in a pipeline. Everyone quickly accepted that the answer to both of these problems was to stop producing faster processors and to start producing more processors. Dual cores, quad cores and many core devices quickly appeared and since that time the software industry has been trying to work out how to deal with the sudden introduction of concurrency.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Achieving High Performance Non-Volatile Memory Access Through "Execute-In-Place" Feature
- Choosing the right memory for high performance FPGA platforms
- Performance optimization using smart memory controllers, Part 1
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
- A Performance Architecture Exploration and Analysis Platform for Memory Sub-systems
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology