English
Chip design’s recycle cycle: Interview with Aart de Geus, chairman and co chief executive, Synopsys
Chris Edwards, New Electronics
September 11, 2012
Some 15 years ago, Synopsys bet on the idea that third party intellectual property (IP) would an important element of the integrated circuit business. Interviewed towards the end of the 1990s, Synopsys' cofounder Aart de Geus – now its co ceo – talked about the problems that chip designers faced as the gap between what Moore's Law could deliver and the number of transistors in a circuit they could realistically deploy per day grew larger. In that interview, de Geus said: "I am totally convinced that reuse is necessary to the advancement of silicon."
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Verification = IP = Verification = IP =... - Part 2 (By Dr. Aart de Geus)
- Co-Design for SOCs -> Software debug shifts to forefront of design cycle
- Co-Design for SOCs -> Cycle-accurate model speeds design
- Synopsys Foundation IP Enabling Low-Power AI Processors
- Revolutionizing Chip Design with AI-Driven EDA
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UPF Constraint coding for SoC - A Case Study