DRAM Controllers for System Designers

By Ron Wilson, Editor-in-Chief, Altera Corporation

Buried somewhere inside the system-on-a-chip (SoC) at the heart of your system is a DRAM controller—or maybe there are two, or four. They are carefully-crafted, tiny blocks of logic that quietly go about their business of connecting the internals of the SoC to external DRAM, requiring no attention from system designers. Or, they wreak havoc, wasting bandwidth, burning energy needlessly, and even allowing data to be corrupted.

The proper operation of the DRAM controller can make the difference between a system that meets its design requirements and a system that runs too slow, overheats, or fails. Either way, ultimately the system design team—who often have little access to information about the controller—will bear the responsibility.

The difference between success and failure arises from the job we ask the DRAM controller to do. The block is far more than just an interface. In advanced system designs, the DRAM controller must mediate between the complex and unpredictable patterns of memory requests dictated by the SoC architecture and system software on one side, and the byzantine timing and obstructive constraints of the DRAM chip design on the other. The difference between good and bad mediation can be a factor of two or more in effective DRAM throughput: a change easily visible in system performance.

To explain these issues—and what system designers can do about them—we need to address three topics. First, we will examine the requirements imposed by the DRAM chip. Then we will discuss the influences of the SoC architecture on memory access patterns, and third, we will explore the structure and function of an advanced DRAM controller. These three sections will lead us to some conclusions about system design.

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