English
System-on-chip technology comes of age
Pushkar Ranade, Senior Director of Process Integration, SuVolta Inc.
EETimes (10/5/2012 1:25 PM EDT)
The silicon transistor continues to be at the heart of post-PC era products like the smartphone and the tablet. The success metrics for the transistor, however, are quite different for these mobile consumer products than they have been in the past. Frequency (clock-speed) was the primary metric in the PC era and the central processing unit (CPU) was the primary chip that drove advancements in semiconductor technology for decades. Form-factor was hardly an influencer and there wasn’t as much of a drive to integrate system-level functionality either on-chip (SoC) or in-package (SiP).
Form-factor, cost and power for a given function are now critical drivers in the mobile market and that in turn has increased the importance of on-chip integration of functional hardware (e.g. power management, computing, audio/video, graphics, GPS and radio). This shift from mostly performance-centric chips to mostly power-constrained chips and the focus on lowering cost and increasing system-level integration is poised to disrupt the traditional semiconductor landscape. SoC technology has been used by fabless vendors and foundries for well over a decade. But it is the rapid proliferation of mobile post-PC products that is proving to be the catalyst for this technology to finally realize its full disruptive potential. Within the last five years, SoC technology has moved from being at the heart of smartphones to enabling tablets and full feature mobile computers like ultrabooks. This article describes the emerging importance of the SoC, its likely technological evolution and its potential impact on the semiconductor industry in a mobility driven age.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- System-on-chip (SoC) design is all about IP management
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- IP Exchange Through Handoff for Easy System-On-Chip Design
- FPGA-based video surveillance comes of age
- Using SystemC to build a system-on-chip platform
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)