Alternative NVM technologies require new test approaches, Part 1
Peter Hulbert, Keithley Instruments Inc.
EETimes (11/13/2012 9:00 AM EST)
Engineers have traditionally characterized floating-gate NAND flash memory using DC instruments such as source-measurement units (SMUs) after pulse generators had programmed and/or erased the memory cell. This approach requires some type of switch to apply the DC or pulse signal alternately to the device under test (DUT). Occasionally, oscilloscopes were used to verify pulse fidelity (pulse width, overshoot, pulse voltage level, rise time, fall time) at the DUT. Measuring the pulse is important because the flash memory state is quite sensitive to the pulse voltage level. The use of oscilloscopes was relatively rare, even in research, however, because the required setup for oscilloscope measurements differed from that for the pulse-source/DC-measure approach. Even when scopes were used for flash characterization, the complexity of measuring the transient current meant that voltage was the only measurement taken while pulsing.
The transition to smaller geometries and multi-bit cells has increased the need for more precise pulse source and measurement for floating-gate NAND flash development. Recently, new instrumentation options for NVM testing have been developed that make it possible to measure the current and voltage simultaneously with a single instrument while applying pulses to a memory device or material. Let’s take a closer look at testing technology for two options: phase-change memory (PCM) and ferro-electric random-access memory (FRAM).
E-mail This Article | Printer-Friendly Page |
Related Articles
- Alternative NVM technologies require new test approaches, part 2
- Facilitating at-speed test at RTL (Part 1)
- An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1
- Paving the way for the next generation audio codec for the True Wireless Stereo (TWS) applications - PART 1 : TWS challenges explained
- Next Gen Scan Compression Technique to overcome Test challenges at Lower Technology Nodes (Part - I)
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)