Alternative NVM technologies require new test approaches, part 2
Peter Hulbert, Keithley Instruments Inc.
EETimes (11/20/2012 9:00 AM EST)
Editor’s note: this is part two of an ongoing series on testing memory.
In Part 1 of this article, I outlined the growing concern among manufacturers of consumer products that incorporate memory devices that floating-gate flash memory would one day soon no longer be able to satisfy their requirements and the search for alternative NVM technologies. I discussed one alternative to flash memory, phase-change memory (PCM), and explored emerging device characterization approaches. Part 2 addresses the testing challenges associated with another emerging NVM technology, ferroelectric memory (FRAM).
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related Articles
- Alternative NVM technologies require new test approaches, Part 1
- Facilitating at-speed test at RTL (Part 2)
- Paving the way for the next generation audio codec for True Wireless Stereo (TWS) applications - PART 2 : Increasing play time
- Next Gen Scan Compression Technique to overcome Test challenges at Lower Technology Nodes (Part - I)
- Specifying a PLL Part 2: Jitter Basics
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow