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Achieving maximum motor efficiency using dual core ARM SoC FPGAs
Michael Parker, Altera Corp.
EETimes (December 1, 2012)
With the integration of dual ARM A9 CPU cores, a complete set of ARM peripherals, the ability to implement in hardware either fixed and floating point signal processing, and unmatched I/O flexibility, the latest FPGA system-on-chip devices can perform what used to require a complete circuit card containing dozens of chips. A perfect example is next-generation motor control.
To get maximum motor efficiency, very fast control loops are used that exceed what processor-only based solutions can implement. The inner control loops, implementing what is known as field-oriented control (FOC), require transforms best performed in floating point. Altera’s low-cost SoC device family, based upon the popular Cyclone architecture, is ideal for this.
One of the ARM A9 cores can implement sophisticated outer loop PID motor control algorithms and apply fine tuning to the inner loop operation. The other can act as a network processor, connecting up to proprietary real-time networking protocols commonly used in industrial applications. Both processors can be used to implement safety critical functions. If the designer needs a different task partitioning between the ARM based software and the FPGA based hardware implementation, it is a simple matter to download new firmware images.
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