The Past, Present and Future of DDR4 Memory Interfaces

The latest DDR4 SDRAM memory standard offers significant performance benefits for SoC designers. Graham Allan, senior product marketing manager for DDR at Synopsys, discusses some of the challenges that design teams face in making the change from DDR3.

DDR4 SDRAM is the latest JEDEC standard for commodity DRAM. It supports a higher range of data transfer rates and lower voltages than previous standards. While JEDEC has specified this latest standard primarily with servers, PCs and laptops in mind, we anticipate manufacturers to favor DDR4 for some portable embedded products, such as tablets. In the long term, DDR4 will be significantly less expensive than specialty low-power memories, such as LPDDR2 and LPDDR3, and will waterfall into mobile applications where the form factor and battery allow.

Overcoming DDR4 Technical Challenges

DDR4 has had a long gestation, taking seven years to standardize within the JEDEC memory standard committees. The technical challenges facing DDR4 have been significant, primarily because the standard must support very high data rates – up to 230 Gbps of maximum bandwidth for a 72-bit wide data bus. DDR4 has approximately 20 new features and as a result is more complex than the previous standard, DDR3. Because of its complexity, DDR4 SDRAM products come to market later than expected, but we expect compatible SDRAMs to start shipping in volume next year.

We have been working with JEDEC for some time to enable us to launch our memory interface IP to coincide with the increase in market demand for DDR4. To meet this schedule, we started to develop DDR4-compatible products before the standard was actually finalized.

In the past, creating a DDR memory interface was an in-house design task of significant complexity. The design team would have to procure a memory controller, assemble the IP components to create a PHY, source I/Os and a PLL from various IP vendors, and then integrate, test and achieve timing closure for the logic and layout. As the DDR data rates increased with DDR2 and DDR3, achieving timing closure without a hard solution for the PHY became more and more difficult using a standard ASIC flow. Design teams quickly recognized the benefits of being able to source a complete, integrated, tested and compliant memory interface solution, incorporating a hard PHY, from a single vendor. Synopsys recognized that offering an integrated DDR memory interface solution would enable design teams to focus their engineering efforts on tasks that added differentiated value to their designs.

We have continued to support a broad range of process technologies with our hard DDR PHY solution, offering an off-the-shelf product that design teams can use with a minimum amount of engineering effort. As a result, Synopsys is a DDR IP market leader with over 330 design wins for its DDR PHYs and controllers.

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