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Integrating large-capacity memory in advanced-node SoCs
Prasad Saggurti, Synopsys
1/14/2013 1:57 PM EST
In today’s system-on-chip (SoC) designs, memory content can consume over 50% of chip area. In addition, the size of individual memories has grown to approximately 40 Mb of contiguous memory. This combined increase can significantly impact the overall power, performance, and area of the chip, as well as manufacturing yield. Successful integration of large-capacity memory in advanced-node SoCs requires the right approach.
Recent advances have made silicon interposer technology an alternative to consider. A silicon interposer consists of additional layers or even a separate chip designed to connect a processor with a separate block of memory. Using this technology in conjunction with through-silicon vias (TSVs), a processor can pass data to and from the external memory without paying the high price of additional pins. Interposer structure consists of multiple layers, however, which adds steps, time, and cost to the fabrication process. Despite the performance boost, the approach is still too expensive to be considered mainstream packaging technology.
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