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Improving the Testability of Complex SoC Designs
by Kathleen Ryan Miller and Martin Funcell
It is well known that testing System-on-Chip (SoC) designs poses technological and economic challenges. With complex SoCs targeted at cost-sensitive consumer applications, especially in the communications arena, it is important to minimize testing costs as much as possible. For this reason, Design-for-Test (DFT) is critical to the success of these chips. In fact, unique and significant test cost reductions can be achieved if DFT can be extended to exploit highly flexible tester resources.
Recent extensions in DFT techniques enable the Concurrent Test (CCT) of circuit blocks within an SoC by isolating target IP cores and ensuring that chip resources are allocated such that the cores can be tested in parallel. To effectively utilize this type of concurrent test, designers should be aware of the procedures, enhanced design automation and test system capabilities needed to implement highly tuned concurrent test.
It is well known that testing System-on-Chip (SoC) designs poses technological and economic challenges. With complex SoCs targeted at cost-sensitive consumer applications, especially in the communications arena, it is important to minimize testing costs as much as possible. For this reason, Design-for-Test (DFT) is critical to the success of these chips. In fact, unique and significant test cost reductions can be achieved if DFT can be extended to exploit highly flexible tester resources.
Recent extensions in DFT techniques enable the Concurrent Test (CCT) of circuit blocks within an SoC by isolating target IP cores and ensuring that chip resources are allocated such that the cores can be tested in parallel. To effectively utilize this type of concurrent test, designers should be aware of the procedures, enhanced design automation and test system capabilities needed to implement highly tuned concurrent test.
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