English
Reducing power in AMD processor core with RTL clock gating analysis
Steve Kommrusch - AMD, Inc.
EETimes (2/4/2013 10:45 AM EST)
Lowering the power consumption of consumer products and networking centers is an important design consideration, and this effort begins with many of the chips that go into these devices. Semiconductor design innovators like AMD want to improve on previous generation designs in terms of faster performance in a given power envelope, higher frequency at a given voltage, and improved power efficiency through clock gating and unit redesign.
With these aims, the AMD low-power core design team used a power analysis solution that helped analyze pre-synthesis RTL clock-gating quality, find opportunities for improvements, and generate reports that the engineering team could use to decrease the operating power of the design. By targeting pre-synthesis RTL, power analysis can be run more often and over a larger number of simulation cycles — more quickly and with fewer machine resources than tools that rely on synthesized gates. The focus on clock gating and the quick turnaround of RTL analysis allowed AMD to achieve measurable power reductions for typical applications of a new, low-power X86 AMD core.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Power analysis of clock gating at RTL
- Reducing Power Hot Spots through RTL optimization techniques
- Achieving Low power with Active Clock Gating for IoT in IPs
- Context Based Clock Gating Technique For Low Power Designs of IoT Applications - A DesignWare IP Case Study
- Sequential clock gating maximizes power savings at IP level
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)