Understand and perform testing for MIPI M-PHY compliance
Chris Loberg, Tektronix
EDN (February 19, 2013)
As MIPI Alliance standards gain increasing acceptance in the world of mobile device design, engineers need to become proficient at electrical PHY layer compliance testing for the higher speed M-PHY serial interconnects. A full set of tests spanning both the transmitter and the receiver are required to validate designs – a task that is made tougher as speeds and complexity increase. Understanding how to setup and perform critical verification and debug tests is critical to any successful M-PHY development effort.
M-PHY Transmitter Testing
The M-PHY specification outlines a comprehensive group of tests designed to verify the various transmitter signaling and timing requirements of M-PHY transceivers. HS mode is used in both Type-I and Type-II modules, which means that the tests related to HS mode are required for all modules. Due to the faster signaling frequency, a number of performance parameters need to be measured on HS mode signals including slew rate, transition time, pulse width, unit interval, differential DC and common mode voltage, minimum eye opening, power spectral density (PSD) and jitter (long term and short term). With the exception of PSD, the other high-speed-mode parameters are either related to time or voltage and can be measured easily using an oscilloscope. While an oscilloscope can be used for PSD, it requires a unique process that will be detailed later in this article.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)