Software patents push design registration limits
Software patents push design registration limits
By Chris Edwards, EE Times UK
May 12, 2002 (6:56 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020510S0016
Changes to the way that designs can be registered and protected have led to a small increase in the number of designs that are being lodged with the Patent Office (PO). But some designers and companies have taken advantage of the new rules to extend what can be protected. Part of the problem is that the Registered Designs Act, based on the EU Design Directive, still only applies to the external look of a product, not internal elements such as circuit boards. Internal elements are protected by non-registered schemes such as copyright. But since December, it has become possible to register external designs that do not have some form of aesthetic appeal, opening up registration to industrial equipment designers. It is a move that lawyers such as Boult Wade Tennant are using to promote design registration as an adjunct to copyright and patent protection. According to Jeremy Philpott, marketing executive for the PO, some designers have taken adva ntage of the fact that it is now possible to register the look of software and icons. He said: "Some registrations have pushed the boundaries. Previously, when someone wanted to protect an icon, they needed to register an entire screen bearing the icon. Now the law protects the pattern." But in terms of number of registrations, Philpott said: "It's very much business as usual." Sarah Merrifield, partner with Boult Wade Tennant, says there is a restriction on an industrial product design if its look is determined entirely by what it does. "Then it is not registrable. It can be functional but [its look] must not be dictated by function," she said. Internal structures and components can still be protected by unregistered rights, says Merrifield, but deliberate copying has to be proved. The advantage of registered designs is that they can be protected against accidental similarities.
Related Articles
- Early Interactive Short Isolation for Faster SoC Verification
- Shift Left for More Efficient Block Design and Chip Integration
- Design-Stage Analysis, Verification, and Optimization for Every Designer
- 5 Steps to Confront the Talent Shortage With IP-Centric Design
- Optimizing embedded software for real-time multimedia processing
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
E-mail This Article | Printer-Friendly Page |