English
Reclaiming lost yield through methodical power integrity optimization
Christian Petersen, Teklatech A/S
EETimes (4/1/2013 10:32 AM EDT)
As designs are moving to 28nm and beyond, designers fully experience the effects of the much higher power density and diminishing effectiveness of decoupling capacitances at these geometries: failures due to dynamic power noise integrity issues is a significant contributor to yield loss in many designs. Synchronous switching and increasing di/dt at advanced process nodes (Figure 1) makes it increasingly challenging for designers to deal with on-chip dynamic voltage drop (DVD) and high frequency electromagnetic interference (EMI). And neither is to be taken lightly; studies have shown DVD fluctuations introduce sizable gate delays causing timing-related yield loss, and EMI from digital switching similarly cause mixed-signal yield loss due to compromised noise integrity.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Reducing Power Hot Spots through RTL optimization techniques
- Effective Optimization of Power Management Architectures through Four standard "Interfaces for the Distribution of Power"
- CPU Soft IP for FPGAs Delivers HDL Optimization and Supply Chain Integrity
- Power Optimization using Multi BIT flops and MIMCAPs in 16nm technology and below
- Optimizing embedded software for power efficiency: Part 4 - Peripheral and algorithmic optimization
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- PCIe error logging and handling on a typical SoC