The Phase Locked Loop (PLL) is an indispensible component in modern electronic systems. Its function is to generate an accurate output signal of frequency equal to, or a multiple of, the input signal frequency. It is mainly used in modulators/demodulators and in clock generation/multiplication. However, when designing a digital communications system on a mixed-signal chip, digital designers tend to avoid PLLs because of their inherent analog nature, and analog designers stay away from them because IDEs involve coding. This article presents a different way of designing a simple PLL.
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