English
Wi-Fi 6 (ax)+BLEv5.4+15.4 Dual Band RF IP for High-End Applications.
Demystifying the PLL
The Phase Locked Loop (PLL) is an indispensible component in modern electronic systems. Its function is to generate an accurate output signal of frequency equal to, or a multiple of, the input signal frequency. It is mainly used in modulators/demodulators and in clock generation/multiplication. However, when designing a digital communications system on a mixed-signal chip, digital designers tend to avoid PLLs because of their inherent analog nature, and analog designers stay away from them because IDEs involve coding. This article presents a different way of designing a simple PLL.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Analysis and Summary on Clock Generator Circuits and PLL Design
- Specifying a PLL Part 3: Jitter Budgeting for Synthesis
- Specifying a PLL Part 2: Jitter Basics
- Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
- Achieving Groundbreaking Performance with a Digital PLL
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UPF Constraint coding for SoC - A Case Study