Chipmakers see early payoffs of design reuse

Chipmakers see early payoffs of design reuse
By David Lammers, EE Times
May 17, 2002 (5:21 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020517S0080

ORLANDO, Fla. — In a testament to design-for-reuse, a 10-member Motorola Inc. design team took a chip to tapeout in a hectic two-and-a-half months, engineers told the Custom Integrated Circuits Conference this past week. Other companies, including NEC Corp. and Texas Instruments Inc., told how they tapped internal intellectual property (IP) repositories to complete system-on-chip designs, indicating that their commitment to IP reuse is starting to pay off.

Bridget Hooser, a design project manager at Motorola's entertainment-solutions division, said her team of 10 designers in Munich, Germany held a kickoff meeting on Jan. 28 of this year, and by April 5 had taped out Amadeus, a 300,000-gate system-on-chip (SoC) for portable MP3 audio players. The April deadline was necessary so that prospective customers could be ready with systems by the Christmas selling season.

"We couldn't have done it without reuse," Hooser said. The corporatewide r euse standards developed within Motorola over the past five years made it possible to meet the tight schedule, she said.

A Motorola team in Singapore transferred an MP3 encoder to Hooser's group in Munich, which "ripped up" the encoder RTL to come up with the key pieces for the decoder engine.

Faith and reason

The Munich team also relied on Motorola's Coldfire Core Technology Center, which provided a soft-IP version of the Coldfire controller and a number of peripherals. While competing MP3 solutions from Texas Instruments Inc. and Cirrus Logic Inc. are based on digital signal processors, the Motorola SoC is based on a 140-MHz Coldfire version 2 processor.

"We actually leaned on the Coldfire Core Technology Center for the initial timing checks," Hooser said. "We proved to others at the Munich design center that you have to go into these projects with a bit of faith in other groups. Not blind faith, of course, but you just can't afford the time for recharacterization."

For its n ext design, aimed at the game machine market, she said the team plans to use a virtual silicon prototyping tool from Silicon Perspectives Corp., recently acquired by Cadence Design Systems Inc., to get place-and-route and timing information at an early stage.

Outside IP also played a role. Motorola contracted with Easics NV (Leuven, Belgium) for the audio-specific virtual components, a relationship that Hooser said was critical to quickly bringing in much-needed audio expertise.

Motorola made an early decision to target the design to the 0.18-micron process at Taiwan Semiconductor Manufacturing Co., and used TSMC-supplied phase-locked loops, low-voltage I/O circuits, D/A converters and other TSMC-developed IP aimed at low-voltage designs.

These days, customers demand working silicon before they will commit to a new chip. About 40 prototypes of the Amadeus chip were obtained by putting it on a multichip wafer at TSMC, at a cost of about $75,000. That sidestepped the expensive alternative of creat ing a full mask set, with the possibility of a mask set respin. The design proved to be working, a mask set was created and the chip is now in early production and has gained at least one customer, Hooser said.

NEC crafts bus IP

Elsewhere at CICC, NEC engineer Kenichiro Anjo said NEC Electron Devices is in the midst of creating internal IP-reuse standards as well as an IP repository that will meld internally developed cores with commercial IP. Toward that goal, NEC has built a high-speed bus for use with its MIPS-architecture processor cores. With the internal code name of NecoBus, the 64-bit bus itself is an IP core, operating at 200 MHz. The bus was used to create a microcontroller, the VR7701, based on a 400-MHz processor core. (For systems-on-chip based on its V-series processor cores, NEC uses the Amba bus from ARM Ltd.)

NEC created an RTL generator to develop wrappers for IP that connects to the NecoBus. "NEC would like to figure out an IP core generator that we could first apply to developing protocols for NEC-standard IP," Anjo said.

The Custom Integrated Circuits Conference itself is in transition. Next year will be the 25th anniversary of the IEEE-sponsored event, which continues to attract a large contingent of analog and mixed-signal design engineers.

The conference has developed another strong track, centered on SoC integration and IP reuse. The organizing committee hopes to boost attendance beyond this year's 400 participants by maintaining the analog focus while putting more emphasis on SoC engineering issues, said Rakesh Kumar, a member of the organizing committee.

The committee voted to move next year's CICC to San Jose, Calif., to attract more Silicon Valley engineers. To put more time between CICC and the Design Automation Conference and the VLSI Technology Symposium, both held in June, the 2003 event will be held Sept. 21-24.