FPGAs offer cost-effective, flexible solutions for remote radio heads
Sumit Shah, Xilinx
EETimes (4/18/2013 2:01 PM EDT)
The explosion of smartphone and tablets is putting exponential strain on wireless networks. Whereas smartphones took about eight years to reach a 10 percent market adoption point, usage jumped to 40 percent in less than three years following the introduction of the iPhone in 2007, according to MIT’s quarterly Technology Review. That rapid growth continues. This user demand has pushed network operators and the OEMs supplying their equipment to cover a broad spectrum of wireless technologies - including GSM, CDMA2000, TD-SCDMA, UMTS and LTE – all while boosting capacity by using new frequencies, higher bandwidth and greater numbers of cell sites to meet the increasing demands.
Competitive pressures and rapid demand are forcing a need to get new products into market at ever faster rates. The newest generation of field programmable gate arrays (FPGAs) – manufactured at the proven 28nm process technology node – offer tighter integration, a reduced BOM costs and increased operational efficiency. By using off-the-shelf intellectual property (IP) and Xilinx 7 series FPGAs and Zynq-7000 All Programmable SoC devices, OEMs can meet shifting market demands while avoiding the huge upfront investment of $20 million or more required to spin a new, fixed architecture device. These FPGA and SoC devices are tightly integrated to deliver more system functions with a focus on programmability, the highest bandwidth and parallel processing available to leverage programmable logic, fewer components, lower power consumption and accelerated design productivity.
E-mail This Article | Printer-Friendly Page |
|
Xilinx, Inc. Hot IP
Related Articles
- Designing remote radio heads (RRHs) on high-performance FPGAs
- Cost-effective two-dimensional rank-order filters on FPGAs
- Extending 8K over a single, cost-effective wire with TICO lightweight compression
- A Cost-Effective Reuse Method of Off-the-Shelf MIMO Wireless LAN IPs with a Nested Spatial Mapping
- A cost-effective and highly productive Framework for IP Integration in SoC using pre-defined language sensitive Editors (LSE) templates and effectively using System Verilog Interfaces
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Synthesis Methodology & Netlist Qualification
- Streamlining SoC Design with IDS-Integrate™