English
Understanding in-loop filtering in the HEVC video standard
Mihir Mody, Texas Instruments
EDN (June 21, 2013)
High Efficiency Video Coding (HEVC) is a video compression standard, a successor to H.264/MPEG-4 AVC (Advanced Video Coding), jointly developed by the ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) as ISO/IEC 23008-2 MPEG-H Part 2 and ITU-T H.265. HEVC promises half bit-rate compared to current de-facto standard H.264 at a similar video quality and is expected to be deployed in a wide variety of video applications ranging from cell phones, broadcast, set-top box, video conferencing, video surveillance, automotive, etc.
The figure below shows the block diagram of the HEVC Video decoder with loop filtering, as shown with loop filtering highlighted. As shown, it is a cascading of two stages - namely de-blocking filtering (DBLK) and Sample adaptive offset (SAO) filtering to remove blocking artifacts causing during video encoding. The next two sections describe these two stages in detail.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Lossless Medical Video Compression Using HEVC
- Understanding - and Reducing - Latency in Video Compression Systems
- Understanding - and Reducing - Latency in Video Compression Systems
- How to map the H.264/AVC video standard onto an FPGA fabric
- Creating multi-standard, multi-resolution video engines using configurable processors
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)