Is Intel within ARM's reach? Pedestrian Detection shows the way
Ranjith Parakkal, Uncanny Vision
EDN (August 20, 2013)
Comparing smart-phone performances - and the SOC and processor cores that drive them - has been a hotly discussed topic of late. More so now, since Intel is trying to challenge ARM in the low-power mobile space with the Atom processor, while ARM is trying to challenge Intel in the server space with the Cortex-A53 and A57. There have been articles written previously comparing the performance of ARM-based phones Vs Atom-based ones - and many benchmarks too- but perhaps not one that compares Cortex-A15 Vs A9 Vs Intel Core i3 from an actual developers perspective. In this post I will try to share my experience working on optimizing computer vision algorithms, pedestrian detection in particular, and compare the performance of the same on the three processors.
Computer vision in layman's terms can be described as analytics that can gleaned from a video or an image. Face detection and recognition are easily understood examples of computer vision.
So why use a computer vision algorithm for benchmarking?
E-mail This Article | Printer-Friendly Page |
Related Articles
- PCIe 5.0 vs. Emerging Protocol Standards - Will PCIe 5.0 Become Ubiquitous in Tomorrow's SoCs?
- What's The Best Way to Verify Your SSD Controller?
- TI's MSP430 vs. ST Microelectronics' ARM Cortex-based processor for battery-powered apps
- What's Next for Multi-Die Systems in 2024?
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)