English
Concurrent hardware/software development
Matt Buckley of Beach Solutions describes a methodology to give software developers access to working emulations of IP blocks generated from the system specification – allowing software and hardware development to proceed concurrently.
Many designers recognise the need to concurrently develop system software and hardware. There are many tools now available that allow a system architect to specify a system design independent of the hardware/software division. However, before implementation can begin a division between the hardware and the software must be specified. At this point the development of software and hardware generally follow separate paths. The hardware and software designers will both be given a copy of the system specification created by the system architect. The hardware and software are then developed independently from each other. The hardware designers verify their design via simulation with test benches that they develop based on the system specification. Similarly the software designers use the system specification to create an abstract model of the hardware system. This abstract model is then used to develop the software design.
Related Articles
- USB Host IP-Core Hardware and Software Concurrent Development
- Concurrent hardware/software development
- Dealing with automotive software complexity with virtual prototyping - Part 2: An AUTOSAR use case
- Validate hardware/software for nextgen mobile/consumer apps using software-on-chip system development tools
- Using unified modeling methods to reduce embedded hardware/software development
New Articles
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- PCIe error logging and handling on a typical SoC
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Synthesis Methodology & Netlist Qualification
|
E-mail This Article | 
|
|
Printer-Friendly Page |