Tiles - An Architectural Abstraction for Platform-Based Design
The relentless pace of Moore's Law has caught up with us again. Design teams still struggling under the weight of system-on-a-chip (SOC) designs composed of hopefully-reusable-next-time IP cores are running head-first into a new challenge-trying to manage the interactions of 50 or more somewhat independent cores throughout the design process. What is needed is a new level of abstraction-a level of hierarchy that reduces the number of objects to something a designer can effectively reason over. Some people call this next level of abstraction the platform, but most platform definitions imply a single "metacore" integrating a critical subset of the desired functions that is then integrated with a set of application-specific peripherals.
Related Articles
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- UPF Constraint coding for SoC - A Case Study
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |