English
Why There's No Need to Fear JESD204B
Jonathan Harris & Ian Beavers, Analog Devices
EEtimes (12/11/2013 03:20 PM EST)
A new converter interface is steadily picking up steam and looks to become the protocol of choice for future converters. This new interface, JESD204, was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.
The JESD204standard applies to analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). It is primarily intended to provide a common interface to FPGAs, but may also be used with ASICs designs.
As the resolution and speed of converters has increased, the demand for a more efficient interface has grown. The JESD204 interface brings this efficiency and offers several advantages over its CMOS and LVDS predecessors in terms of speed and size. Designs employing JESD204 enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count, which leads to smaller package sizes and a lower number of trace routes that make board designs much easier.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow