By Ron Wilson, Editor-in-Chief, Altera Corporation
January, 27, 2014
We have entered the age of heterogeneous multiprocessing. In high-performance computing applications, architects are adding hardware accelerators to the multicore CPU clusters in their huge supercomputers. At the other end of the spectrum, designers of embedded and mobile systems are moving critical code loops into hardware to slash energy consumption. Everywhere in between, embedded-system designers are looking at multicore SoCs with on-chip accelerators or programmable graphics processors, or at FPGAs with integrated CPU cores, and wondering if such chips could be the best route to adequate performance at minimal energy for their application. Such architectures offer a way forward even as the promises of increasing uniprocessor performance and of aggressive multithreading fade. But heterogeneous multiprocessing brings its own challenges. For software developers there are issues such as scheduling, synchronization, and programming models. For hardware developers, one of the key questions is how to attach the accelerator to the rest of the system. That is the question we will take up here.
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