SoC interconnect architecture considerations

Rahul Gulati , Prashant Karandikar , Vasant Kumar Easwaran , Prithvi Shankar & Mihir Mody (Texas Instruments)
EDN (March 21, 2014)

The SoC interconnect architecture has a huge impact on what a given SoC can deliver. This is a huge topic of interest for the SoC designers. This is hardly surprising, with the SoC designs nowadays getting more and more communication-centric. Most of the SoCs nowadays consist of multiple processors, hardware accelerators for specific tasks, on chip memories, several standard interfaces to connect to real world devices and custom Intellectual Property (IP) blocks.

Given that many SoCs nowadays are comprised of a plethora of such blocks, the interconnect architecture can be a key differentiator among the SoCs. Traditional communication architectures were bus-based architectures with a central crossbar responsible for arbitration among the various masters connected on the bus and the protocol specific communication between the masters and slaves on the bus. However, given the number of increasing IP blocks that need to be integrated on an SoC, there has been a shift towards Network-On-Chip (NoC) communication architectures. These NoC architectures use the packet switched network concepts for interaction among the various initiators and targets.

Application specific NoC architectures are needed to support applications that require high performance and low power consumption. Complex applications, such as in-car navigation systems combined with dual rear seat entertainment systems, in-car forward camera analytics running with a number of vision algorithms, Ethernet surround view application, etc, are now implemented in consumer and automotive electronics, which must provide high performance with low energy consumption. Optimizing for these applications early in the design flow can potentially yield better optimization results. The NoC architecture is typically customized for each application or a limited range of target applications, in order to achieve optimal performance and power trade-off.

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