Security demands hardware improvements
Chris O'Reilly, Broadcom
EDN (April 04, 2014)
Fast, reliable network connectivity is at the heart of business today – powering critical infrastructure systems, internal business operations, customer-facing communications and home-based entertainment services. But it’s not only system performance that keeps network managers awake at night. As more people embrace multiple connected devices through a wide range of applications, security vulnerabilities are top-of-mind for both network managers and network hardware designers. As the type and scope of network traffic continues to evolve, so does the complexity of security threats. It is more important than ever to address greater levels of security at all points within these complex and varied network environments.
Critical infrastructure networks (such as financial transactions and power plants) clearly require increased protection. But even ‘lower level’ networks must take greater care to protect personal information that may become exposed during everyday transactions. Emerging network platforms in the cloud, home gateways, and mobile enterprise have opened additional avenues for threats against data security and system performance.
Even the simple process of uploading a photo to the cloud – much less using it to transmit enterprise data – requires the image to be secure at the device level, in the cloud, and at all points between as it traverses the network itself.
As security threats continue to evolve and network providers vie for customers interested in high-performance, seamless security at every point within the network, innovation at the silicon level is critical. High performance security features – integrated into silicon hardware – allow network managers to more thoroughly and more intelligently inspect, encrypt, authenticate and secure Internet traffic at wire speeds.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)