Performance optimization using smart memory controllers, Part 1

Puneet Pal Singh, Love Gupta, Gaurav Gupta, Freescale
EDN (May 16, 2014)

In a System on Chip (SoC) environment, multiple digital and analog modules are integrated together on a single chip along with processors and various type of memories which are managed by conventional memory controllers. These controllers manage data flow between peripherals and memories and between processor and memories. Figure 1 explains the basic data flow between processor and the memory.

Figure 1. Basic Data Flow between Microprocessor and Memory

Need for Smart Memory Controllers
Steady advancements in technology have lead to nearly 60% improvements (YoY) in microprocessor performances. However, memory performance improvements are comparatively slower[1]. Consequently, the relative slower performance of the memories and their controllers impacts the overall performance of the SoC. For example, as the rate of executing instructions continues to increase, the demand for memory bandwidth has increased proportionately. Besides this, IC behavior depends upon PVT (Process, Voltage, Temperature) conditions and operating frequency. Change in PVT conditions may lead to synchronization and handshaking issues between processor and the memory, resulting in poor performance of the SoC. A smart, highly configurable memory controller can address the above issues.

Various features that a smart memory controller allow to be configured for getting an optimized SoC performance and mitigate the above mentioned issues are:

Read Wait States control (RWSC)
APC (Address Pipeline Control)
Cache buffers and Prefetching
Address Remapping

In this paper, we will discuss the first two features of memory controllers. The remaining two, viz. Prefetching and Address remapping features will be discussed in the subsequent papers.

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