Process Detector (For DVFS and monitoring process variation), TSMC 12FFC
Challenges in LBIST validation for high reliability SoCs
Abhinav Gaur & Gaurav Jain (Freescale)
EDN -- July 19, 2014
Logic built-in self test (LBIST) is being used in SoCs for increasing safety and to provide a self-testing capability. LBIST design works on the principle of STUMPS architecture. STUMPS is a nested acronym, standing for Self-Test Using MISR (Multiple Input Signature Register) and Parallel SRSG (Shift Register Sequence Generator). It consists of a Pseudo Random pattern generator (PRPG) for generating the test stimuli for the scan input, and Multiple Input Signature Register (or MISR) for collecting the scan output. If the final MISR signature matches with the golden or expected MISR signature, the LBIST status is “Pass”.
For any SoC that provides the LBIST functionality, there will be a need for tester patterns for production, for checking whether the LBIST is working properly on each of the samples being delivered to the customer. This paper will discuss the various challenges while developing these LBIST tester patterns for production, and ways of creating such patterns efficiently.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- Reliability challenges in 3D IC semiconductor design
- Bulletproofing PCIe-based SoCs with Advanced Reliability, Availability, Serviceability (RAS) Mechanisms
- Hitless I/O: Overcoming challenges in high availability systems
- Opportunities and Challenges for Near-Threshold Technology in End-Point SoCs for the Internet of Things
- Challenges in verifying PCI Express in complex SoCs
New Articles
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- An Outline of the Semiconductor Chip Design Flow
- Synthesis Methodology & Netlist Qualification