English
Wearing the Architecture: Evolution in Wearable Electronics
By Ron Wilson, Editor-in-Chief, Altera Corporation
The growth of wearable electronics—whether for biometrics, communication, or augmented reality—extends the concept of an embedded system into new, unexplored territory. Putting sensors and output devices on or in the human operator conjures up the coined word cyborg: a merging of human faculties with embedded systems.
Just as wearables open new vistas for applications, they demand new perspectives in embedded architecture. A cluster of sensors in an adhesive patch or an ingestible lozenge is completely isolated from conventional power, ground, and I/O connections. Yet to achieve tiny size and near-zero energy consumption, that little cluster may be more-then-conventionally dependent on local signal-processing, storage, and wireless connectivity. It is a paradox architects must untangle.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Intel FPGA Hot IP
Related Articles
- The basics of designing wearable electronics with microcontrollers
- Multi-Core Processors: Driving the Evolution of Automotive Electronics Architectures
- Opto-electronics -> High-density fiber-optic modules eye next-gen switching architecture
- Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning
- How control electronics can help scale quantum computers
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)