English
High-Reliability FPGA Designs
Joe Mallett, Synopsys
10/15/2014 11:40 AM EDT
Over the past few years, the need for high-reliability and high-availability systems has expanded past military and aerospace into the datacenter, onto the industrial floor, and into medical devices. This challenges FPGA developers to build highly reliable systems to address the growing market needs. There are several special design techniques that can be used to detect in-system errors and recover to correct operation.
Soft errors
With increasing integration of electronics for things like engine control, braking systems, and collision avoidance in automobiles, there is little-to-no margin for soft errors that could result in harm to humans. There are other applications that may not endanger lives, but still require safe operation, like medical equipment, industrial control, and high-availability communications equipment that could be very costly when a system fails. The challenge is that all electronic equipment can be affected by radiation-induced "glitches," advanced process technologies, and complex system implementation.
Today, many FPGAs are used to implement critical functions in electronic systems, and, as a result, it is critical to make sure they operate correctly and reliably. Radiation in the atmosphere can cause unstable conditions that result in an unwanted transient signal in the combinatorial logic of an FPGA. If this transient -- known as a single event upset (SEU) -- is propagated throughout the system, it could potentially cause a failure.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Synopsys, Inc. Hot IP
Related Articles
- Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs
- Creating highly reliable FPGA designs
- General Partitioning Guidelines for Validation of Large ASIC Designs On FPGA
- Are Your FPGA Designs Secure?
- Implementing high Speed USB functionality with FPGA- and ASIC-based designs
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)