Safeguard your FPGA system with a secure authenticator
Michael D'Onofrio, Maxim Integrated
embedded.com (November 23, 2014)
In the 21st century counterfeiters increasingly target electronic devices because the profit from selling copied electronics can be very rewarding. Furthermore, certain types of electronic components like FPGAs—and especially their attached peripherals/subsystems—can be relatively easy to copy. Consequently, all too often end users cannot be sure that they are using genuine OEM equipment. This can be quite disappointing when the end user encounters substandard counterfeit devices, items that break down easily or do not work properly. But perhaps more gravely, consider the implications of using a substandard or inaccurately calibrated surgical device. This can be deadly.
What about OEMs who see parts of their products being counterfeited? OEMs face revenue loss when their goods are counterfeited in the market. This phenomenon is not limited to emerging markets. Indeed, the supply chains for many electronic goods stretch worldwide, so counterfeit goods can find their way into virtually any supply chain.
This article outlines the general problems that counterfeiters pose for OEMs and end customers. It then turns to FPGA systems and explains how OEM system designers can address their concerns about the counterfeiting of FPGAs. Designers can secure their FPGA bitstream, protect IP, and prevent attached peripheral counterfeiting through use of secure authentication ICs that implement a SHA-256 or ECDSA algorithm.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Setting up secure VPN connections with cryptography offloaded to your Altera SoC FPGA
- FinFETs, Analog Circuits, and Your Next System Design
- Are Your FPGA Designs Secure?
- Anti tamper real time clock (RTC) - make your embedded system secure
- Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)