English
Automatic ASIC-to-FPGA Conversion
Joe Mallett, Synopsys
EETimes (1/15/2015 01:55 PM EST)
Performing ASIC-to-FPGA clock tree conversions by hand is difficult and time-consuming for designers; the use of automated gated clock conversion makes this task much less challenging.
As electronic companies design today's leading-edge ASICs, increasing costs and shortening development schedules are requiring ASIC designers to develop an early prototype. Prototypes are used to help accelerate hardware and software schedules and complete system verification. Companies often fulfill their prototyping requirements with platforms based on FPGAs, which provide developers the opportunity to have a hardware platform early in the design cycle.
Using a prototyping platform for initial software development has become standard practice that allows for faster software development and debug. Development work can be compiled and debugged on real hardware allowing needed bug fixes to be integrated early in the development cycle. In addition, the verification teams can utilize the prototyping platform to accelerate verification by allowing the testing of designs on FPGA hardware platforms very early in the process, thereby gaining a significant advantage in advance of final silicon becoming available.
All of this leads to the fact that many ASIC teams are tasked with creating an FPGA-based prototype to enable hardware-based debug, test, and early software development. In most cases, the design team provides nightly or weekly builds of the most current prototype to the software development and verification teams. These ongoing changes to the ASIC design mean that the hardware designers require some method of generating corresponding updates to the prototyping platform.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Synopsys, Inc. Hot IP
Related Articles
- Resolution of Interoperability challenges in Automatic Test Point insertion across different EDA vendors
- Automatic C-to-VHDL testbench generation shortens FPGA development time
- Two methodologies for ASIC conversion
- Automatic shape-based routing to achieve parasitic constraint closure in custom design
- Analog IP Porting by Topology Conversion and Optimization
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)