English
Bluetooth low energy v6.0 Baseband Controller, Protocol Software Stack and Profiles IP
FinFET impact on dynamic power
Arvind Narayanan, Mentor Graphics
EDN (March 11, 2015)
FinFET transistors are now in production at the major foundries, having gone from drawing board to products on the shelf in record time. FinFET adoption has been growing steadily because they deliver better power, performance, and area compared to their planar counterparts. This makes them very compelling for smartphones, tablets, and other products that require long battery life and snappy performance. Figure 1 shows the advantages in speed, power usage, and density of TSMC’s 16nm FinFET process over two other processes.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- A need for static and dynamic Low Power Verification
- How to manage dynamic power in a microcontroller using its non-maskable interrupt
- Employ dynamic power reduction in an ASIC
- Pulse-latch approach reduces dynamic power
- Using dynamic run-time scheduling to improve the price-performance-power efficiency of heterogeneous multicore SoCs
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology