English
Improving analog design verification using UVM
Mike Bartley, Test and Verification Solutions
EDN (March 23, 2015)
As technology becomes more integrated into our everyday life, our chips need to better communicate with the analog world. Most modern system on chip (SoC) designs therefore contain analog and mixed-signal (AMS) elements integrated with digital components. According to Sandip Ray of Intel, AMS elements currently consume about 40% of the design effort, and an estimated 50% of errors in recent chips that require a redesign are due to bugs in the AMS portion of the design [1].
This increase in AMS content in silicon creates several verification challenges: how do we verify the analog design itself, its integration with the digital, and whether the combination achieves the intended overall function? However, there is no standard or even widely adopted approach to this despite the continuous increase in analog content. One potential route is via an efficient, reusable AMS verification approach using the Universal Verification Methodology (UVM) outlined below:
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Out of the Verification Crisis: Improving RTL Quality
- Design patterns in SystemVerilog OOP for UVM verification
- Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
- Improving Performance and Verification of a System Through an Intelligent Testbench
- Power of UVM's Command Line Argument Usage in Verification Test benches
New Articles
- Understanding MACsec and Its Integration
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Synthesis Methodology & Netlist Qualification
- Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution