English
Automating IP Handling in a Multi-Source World
Joe Mallett, Synopsys
EETimes (4/7/2015 09:00 AM EDT)
Companies designing new FPGA-based products are subject to ongoing market pressure to do more with less and achieve higher returns. The result is engineering teams having to deliver more with fewer resources, reduced design tool budgets, and shortened time-lines to get new products to market. This has led companies designing complex FPGAs to move increasingly toward licensing IP cores for the majority of the building blocks comprising their designs instead of building their own custom versions in-house. Selecting the right IP cores is the fundamental challenge of this developing paradigm, and the process of evaluating and presenting it is as important to the purchaser as it is to the developer.
There are many sources of IP cores -- third-party, FPGA vendors, and internally developed -- and being able to import and synthesize these cores is a key requirement.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Synopsys, Inc. Hot IP
Related Articles
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- System Verilog Assertions Simplified
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
- Design Rule Checks (DRC) - A Practical View for 28nm Technology