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1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (12nm)
Library promotes common standard for design properties
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Library promotes common standard for design properties
By Michael Howard, C-Cube Microsystems, EE Times
August 19, 2002 (10:38 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020815S0008
The Open Verification Library (OVL) provides a standard set of assertion modules that not only enhance simulation but also ease the adoption of RTL formal verification tools. The OVL assertion modules are written in standard HDL, so the user is not required to learn a proprietary language in order to specify design behaviors for verification. Moreover, the same assertions can be used in both simulation and in the BlackTie formal verification environment.
The automatic-check benchmark data shows that formal verification with BlackTie can be applied from the block level all the way up to full chip. Further, BlackTie's automatic checks eliminate the need to create testbenches or assertions to exhaustively verify common design functions.
The OVL is an open-source initiative, and the library can be freely downloaded from the Web (www.verificationlib.org).
The latest release, version 1.1. 0, is a set of 26 Verilog assertion monitor modules. More assertion modules will be added in the next release.
Complete documentation of the assertions in the library is provided on the OVL Web site. Because the library is user-community-extensible, anyone can add to, modify and redistribute the OVL under the terms an open-source license.
The OVL/Assertion Committee oversees changes and extensions to the OVL version posted on the Web. Users can go online to offer their opinions and suggestions to the committee, which is part of the Accellera standards organization (www.accellera.org).
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