High Speed Data Recorder

Rudolf Usselmann, ASICS World Services, LTD.
June 15, 2015

Abstract

A new IP Core from ASICS World Services, provides a complete high speed data recorder, in one easy to use block.

Introduction

Based on our 4 port 12G SAS Host IP controller, we have developed a recorder IP Core. The goals for the recorder where to provide an easy to use solution, without the customer needing to understand storage protocols in depth and figuring out how to use and program the SAS host controller. We wanted to provide a block which literally accepts a data stream and is controlled by a couple of signals that are easy to understand on one side, and directly attaches to SSDs on the other.

Description

There are different requirements for data recorders. Some require high bandwidth, others large storage, and yet others need continues recording. All of these requirements are addresses by our SAS based recorder.

This recorder can utilize up to 4 SAS ports simultaneously, providing high bandwidth and increased storage capacity. The actual number of ports used can be selected at compile time. Each SAS port is capable of interfacing with a 12G SAS SSD, providing a 1.2 GBytes/sec interface. The recorder can easily sustain a bandwidth of up to 4.8 GBytes/sec. Internal control logic automatically issues write instruction to the drives, and ensures maximum utilization of the SSD drives. The SAS Initiator IP Core implements SAS complaint link, port and transport layers.

The SAS physical interface is also fully integrated. Complete SAS PHY is implemented in the FPGA fabric, utilizing Xilinx high speed transceivers. It includes all required logic for a complete PHY, such as OOB Signaling and Speed Negotiation.

The user application interface consists of a AXI compatible stream interface and simple control signal to initiate recording. It also allows user application to partition drives to record different signals on to dedicated areas, or to contentiously record a data stream.

The retrieval of data is just as simple, a stream interface in the opposite direction allows the user application to retrieve the stored data. Here too, the user application can specify a specific location and size, or retrieve the entire stored contents.

About the Author

Rudolf Usselmann is the General Manager of ASICS World Services, LTD. He is also hands-on involved in planning and design of IP Cores. Mr. Usselmann has been a chip designer for over 25 years.

ASICS World Services, LTD, was founded in 1999, immediately starting to offer various products and services. Since then ASICS World Services has established a world wide reputation for profession highest-quality IP Cores with flexible licensing at a low cost. ASICS World Services also offers a wide variety of custom design services. For more information, please visit: http://www.asics.ws