English
Estimate power at RTL to identify problems early
Aniruddha Gupta & Himani Grover (Freescale)
EDN (August 05, 2015)
SoC power consumption is a key differentiating feature. The initial estimated power of the design is often less than the power use seen on silicon. This happens because there is no power estimation flow available that can accurately correlate power estimation results with the silicon results. Also, for parts that involves a lot of new design features & IP blocks, the exact gate count details are difficult to predict early in the flow.
In addition to more accurate power-estimation flow, there is a need for RTL-stage power estimation, offering the opportunity to reduce power early in the design. This paper discusses the basics of power estimation, and a power-estimation flow at RTL level, which should be known to everyone designing IP & SoCs.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Throttle IP Core Power Dissipation: Use RTL Power Analysis Early and Often
- Reducing Power Hot Spots through RTL optimization techniques
- Guidelines for early power analysis
- Reducing power in AMD processor core with RTL clock gating analysis
- Memory solution addressing power and security problems in embedded designs
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)