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NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
PLL Subsystem architectures for SoC design
Sunil Deep maheshwari , Prashant Bhargava & Shreya Singh (Freescale Semiconductor)
EDN (August 21, 2015)
Because of the cornerstone importance of PLLs to an SoC design, this article considers the various challenges in the design of PLL subsystems, and discuss architectural solutions.
The PLL subsystem is expected to drive the clocks of the SoC. Therefore, one needs to make sure that the system is able to recover after an unexpected event occurrence, say, failure of the input clock, malfunctioning of the analog block, etc. Some of the necessary architectural features include:
- In-built Clock Monitor Unit to observe changes in clock frequency.
- Error reporting mechanism
- Back-up clock selection feature to allow switching to the fallback clock.
- Progressive clock switching – in the event of a clock switch-off.
- Security of PLL subsystem
- System level understanding to make the sub-system adaptable to the overall system and working conditions.
Subsequent sections describe these challenges more thoroughly.
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