Hybrid Emulation: It's about time!

Doug Amos, One-Man-Army FPGA Consultant
EETimes (8/31/2015 04:25 PM EDT)

Given the critical importance of software as a differentiator in SoC-based products, doesn't the software team deserve the best tools available?

What's this article about?

This article scrutinizes the long-foretold ability for virtual platforms to be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. We explore how this has evolved from a neat idea to become Hybrid Emulation -- a practical solution for today's SoC hardware and software teams.

Since the advent of transaction-level modeling, it has been possible to create a virtual platform of a CPU sub-system, which trades-off accuracy for speed in order to provide an early target to test software. Traditionally, the make-or-break of such virtual platforms was the availability of SystemC models for the various components; it would simply take too long to generate a trustworthy model for, say, a new co-processor, so the benefit of early software simulation was lost. The growth of SystemC model libraries for popular functions -- such as ARM's Fast Models -- has helped to fill those gaps, but what of the new functions unique to the new SoC? One proven solution is to implement such functions in an FPGA-based emulation platform such as Aldec's HES, and then link that into the virtual model via SCE-MI transaction-level interfaces.

This article will explore seven different use modes for such hybrid emulation platforms. As part of this, we'll use examples from Aldec Inc. to explain how the hybrid combination of virtual platform and FPGA hardware offers a "best-of-both-worlds" approach. We discuss certain practical constraints and also how success is largely a matter of time -- the timing accuracy required, the time taken to create the hybrid, and the time saved by doing so.

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