All you need to know about MIPI D-PHY RX
Love Gupta, Freescale
EDN (September 08, 2015)
MIPI D’Phy, a physical serial communicating layer connecting the application processor to the display device or the camera, offers advantages as the physical layer.
The MIPI (Mobile Industry Processor Interface) alliance is a non-profit organization that establishes standards for hardware and software interfaces in mobile devices. Its vision is to develop the world’s most comprehensive standard set of interface specifications for mobile and mobile influenced products which will maximize design reuse, drive innovation, reduce time to market and will help in interoperability of products from various companies.
MIPI D’Phy is a physical serial data communication layer on which the protocols like CSI (Camera Serial Interface), DSI (Display Serial Interface) runs. It physically connects the camera sensor to the application processor (for CSI) and application processor to the display device (for DSI) as shown in the figure above.
D’Phy is a high speed, low power, source synchronous physical layer which is best suited for power hungry battery operated devices due to its power efficient design. It includes in it both the high speed and low power modules which helps in achieving power efficiency. The payload data (image data) uses the high speed modules whereas the control and status information is send (between camera/display device and the application processor) with the help of low power modules(utilizing low frequency signals). It has a peculiar ability of sending the high speed and low power data in the single packet burst. The low power modules help in achieving power savings and the high speed modules help in achieving the much needed higher bandwidth requirement for the High definition picture quality data signals.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Towards Self-Driving Cars: MIPI D-PHY Enabling Advanced Automotive Applications
- A design of High Efficiency Combo-Type Architecture of MIPI D-PHY and C-PHY
- Providing USB Type-C connectivity - What you need to know
- USB 3.0 - Everything you need to know
- Analog switches in D-PHY MIPI dual camera/dual display applications (Part 2 of 2)
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)