English
7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Best design practices for DFT
Gunjot Kaur , Sidhant Goel & Mayank Parasrampuria (Freescale)
EDN (October 14, 2015)
SoC sub-components (IPs) generally come from various sources – internal and external – and with that it has become necessary that designers ensure the RTL is testable. If the RTL has testability issues, test coverage goals can’t be met and the RTL needs to be modified, which means several iterations of synthesis, verification, and Automatic Test Pattern Generation (ATPG).
Here we will discuss the basic design practices to ensure proper testability.
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