System on Chip, or System on Chips: The Many Paths to Integration
By Ron Wilson, Altera
System on chip means putting everything you can on one die. Only lack of technology, major process incompatibility, or physically running out of real estate have seemed valid excuses for taking a multi-die approach to integration. But these ideas are ending.
Today new options, including lower-cost multi-die packaging, novel uses of high-speed serial transceivers, and even non-electrical interconnect are opening new possibilities for partitioning system cores across multiple dice. Architects can contemplate ideas that bandwidth limitations or power budgets would have precluded before. This means new combinations of performance, efficiency, and compactness well beyond today’s state of the market.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Altera Hot IP
Related Articles
- A cost-effective and highly productive Framework for IP Integration in SoC using pre-defined language sensitive Editors (LSE) templates and effectively using System Verilog Interfaces
- Hot Chips: the puzzle of many cores
- Using co-design to optimize system interconnect paths
- Continuous integration of complex reconfigurable systems
- How designers can survive the embedded multiprocessor revolution
New Articles
- The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
- Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
- Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
- How the Ability to Manage Register Specifications Helps You Create More Competitive Products
- EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
Most Popular
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- PCIe error logging and handling on a typical SoC