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Design, Test & Repair Methodology for FinFET-Based Memories
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys
The advent of FinFET-based memories presents new memory test challenges. This white paper covers the new design complexities, defect coverage and yield challenges presented by FinFET-based memories; how to synthesize test algorithms for detection and diagnosis of FinFET specific memory defects; and how incorporating built-in self-test (BIST) infrastructures with high-efficiency test and repair capabilities can help to ensure high yield for FinFET-based memories.
If you wish to download a copy of this white paper, click here
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