Enable IoT ASIC Design Using Platforms
Pradeep Sukumaran, Sr. Solutions Architect, Open-Silicon
EDN (January 07, 2016)
The Internet of Things (IoT) hype is now getting real. This, in turn, is creating the opportunity to move from off-the-shelf chip designs to custom silicon. The key to creating cost-effective, custom silicon for the IoT will be the platform approach.
It is fair to say that IoT is now living up to the hype. There has been a significant uptick in activity over the past year with the IoT ecosystem, the end customers, the hardware and software vendors, the system integrators and the startup community. Yes, IoT implementations are definitely happening, although not at the same rate as first expected, and certainly not the 50 billion devices or a trillion sensors by 2020. Nevertheless, it is an encouraging sign for ASIC design companies as they become an important and differentiating cog of the IoT supply chain.
Historically the industry has been churning out custom silicon for the cloud side of IoT for years, specifically in the networking, telecommunication, storage and computing arenas. However, devices on the edge of the IoT network have, so far, been designed using stock components rather than custom silicon. Using a platform approach to custom silicon design can substantially enhance functionality and offer greater design flexibility.
An IoT edge device typically performs three functions: sensing/actuating, processing and communication. Depending on various factors, like cost, schedule and application, a custom silicon implementation in these IoT edge devices could be a low-end/low-cost, mid-level or highly integrated solution. Below is a representation of typical ASIC configurations of each type. In all of these cases, ultra-low power is a default requirement.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- ASICs Bring Back Control to Supply Chains
- Partitioning to optimize AI inference for multi-core platforms
- A comprehensive approach to enhancing IoT Security with Artificial Intelligence
- Understanding the Deployment of Deep Learning algorithms on Embedded Platforms
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)