English
High bandwidth memory (HBM) PHY IP verification
Ankit Sheth & Jignesh Oza (eInfochips)
EDN (February 23, 2016)
Memory systems have evolved a lot in the previous few years due to advancements in fabrication technology. High Bandwidth Memory (HBM) is an example of the latest kind of memory chips which can support low power consumption, ultra-wide communication lanes, and stacked configurations. HBM subsystems involve different types of memory controllers (full-speed, half-speed), HBM PHY, and HBM DRAM. The HBM subsystem is suitable for applications involving high performance graphics and computing, high end networking and communication devices, and memory-hungry processors. Because of their critical end-application role, it is crucial to verify all design components involved in HBM subsystems. Here, we will discuss the role of the HBM PHY, along with the major verification aspects/challenges.
Introduction
The HBM PHY is a key element in an overall HBM system solution. HBM PHY generally receives HBM DRAM row-col commands, data, parity, etc. from memory controllers through DFI interfaces and passes them to HBM memory along with the use of HBM DRAM interface. It deals with two different interfaces and supports multiple frequency ratios for DFI interfaces. HBM PHY is ideally required to support all HBM memory features like frequency ratios, data rates, memory sizes, pseudo channel modes, legacy modes, DBI,DM etc. HBM PHY can be verified at the sub-system level and block level with different, vendor-specific memory controllers and HBM memories.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- High Bandwidth Memory (HBM) Model & Verification IP Implementation - Beginner's guide
- Design Considerations for High Bandwidth Memory Controller
- How to accelerate memory bandwidth by 50% with ZeroPoint technology
- Achieving High Performance Non-Volatile Memory Access Through "Execute-In-Place" Feature
- Choosing the right memory for high performance FPGA platforms
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- UPF Constraint coding for SoC - A Case Study
- Dynamic Memory Allocation and Fragmentation in C and C++
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)