Careful IP Integration Key to First-Pass Silicon
Vamshi Krishna, Sr. FAE & IP Solutions Manager, Open-Silicon
EETimes (4/25/2016 00:00 AM EDT)
Follow these four aspects of IP integration to allow first-pass ASIC silicon when using IP from multiple vendors.
Most ASIC companies today rely on third-party IP in building a custom ASIC/SoC. While ensuring convenience in terms of flexibility, schedule, and cost effectiveness, however, this approach can also present challenges. IP companies, although they adhere to common Industry standards, typically follow different IP development processes, apply different quality benchmarks, and provide different deliverables. The fact that each IP block is unique with respect to its function creates even more differentiation. All this variability makes it difficult to assemble an ASIC using IP from multiple sources and achieve first-pass silicon.
It is possible to achieve first-pass silicon, however, by following a careful integration process. Here are four aspects that ASIC design companies have to consider when using IP blocks from different vendors.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success
- Mastering Key Technologies to Realize the Dream - M31 IP Integration Services
- The common silicon issues in analog IP integration
- Silicon Qualified SuperViC: the only way to safe SoC integration
- Integration key to multimode era
New Articles
- Why RISC-V is a viable option for safety-critical applications
- Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
- What is JESD204B? Quick summary of the standard
- Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
- Analysis and Summary on Clock Generator Circuits and PLL Design
Most Popular
- System Verilog Assertions Simplified
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Method for Booting ARM Based Multi-Core SoCs
- An Outline of the Semiconductor Chip Design Flow