Hardware/software codesign needs new business model

Hardware/software codesign needs new business model
By Frank Schirrmeister , EEdesign
September 23, 2002 (8:21 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020923S0083

With mask costs for advanced technologies approaching millions of dollars, the simplest mistake can be disastrous. One flaw puts the nonrecurring engineering costs at risk of indeed "never returning, ever" -- giving a special meaning to the term NRE.

In light of the increasing risk and inflexible nature of hardware design, more and more of the product differentiation and flexibility has been moved into the embedded-software design. IBS predicted in July 2000 that the effort spent per design on embedded software would surpass the effort spent on hardware already in 0.15-micron designs.

The design community and EDA industry started addressing this situation from a technology perspective some time ago. Hardware/software co-verification tools became available to connect the hardware and software design teams earlier in the design cycle.

Moving system-level design to higher levels of abstraction has led to more advanced technology in the area o f hardware/software co-design. The development of these hardware/software tools was funded with the expectation that a new, untapped market of software engineers would join existing hardware users on the EDA customer lists. But that has not yet come to pass.

Quite accurately, Dataquest has begun to differentiate between system design styles. Silicon-focused system-on-chip (SoC) design seeks the competitive advantage in the hardware, whereas embedded design differentiates via software.

Price tags an issue
Some estimates say there are roughly 10 times more software designers than hardware designers. However, these software designers will no doubt turn pale when given an EDA price list -- they are accustomed to prices in the four-digit range, if that high. Even though the average selling price in the embedded space is increasing, according to Dataquest, the traditional EDA business model, devised around specialized hardware design, falls short when trying to address the requirements of the em bedded-software space.

The number of "hardware-aware software designers" has not been high enough to create enough market pressure for efficient design solutions, leaving those technologies -- although advanced and available -- to languish in the market. However, their numbers are now increasing significantly. The advent of "full application platforms" like OMAP from Texas Instruments or Nexperia from Philips signal a time when the majority of design starts incorporate multiple processor cores on a single chip.

The complex pipeline and cache effects in these designs have a major impact on the performance of firmware, middleware and, often, even the actual application software. As a result, an increasing number of software designers have to become "hardware-aware."

Meanwhile, the traditional EDA business model has assumed a symmetric market and is not prepared to address model exchange efficiently. Both the hardware and the software designer have to buy the same tool to exchange models. However, while the hardware designer is creating a system-level virtual prototype of the SoC, the software designer is consuming this model for early hardware-aware software development. Two different design mentalities focus on different tool use models.

To resolve this disconnect, smarter business models must be introduced. The EDA industry needs to enable hardware designers to integrate system-level virtual prototypes as a run-time model into the software-development infrastructure they are providing for the SoC. Together with compiler and debugger, the system-level virtual prototype enables early hardware-aware software development at a price point acceptable to the embedded space.

With these two obstacles out of the way the future looks bright for hardware-aware embedded-software development.

Frank Schirrmeister is vice president of business development at Axys Design Automation in Palo Alto, Calif. and can be reached at fs@axysdesign.com.