LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
10 FPGA Design Techniques You Should Know
Adam Taylor, Head of Engineering Systems at E2V
7/14/2016 07:00 AM EDT -- EETimes
Regardless of whether you are using VHDL, System Verilog, or a different design capture language, there are a number of universal design techniques with which FPGA engineers should be familiar, from the very simple to the most advanced.
In this column we'll take a look at 10 I believe to be important and discuss why I feel this way.
Index
- Introduction
- State Machine Design
- Basics of FPGA Math
- First In, First Out (FIFO) Buffers
- The CORDIC Algorithm
- Metastability Protection
- Discrete & Fast Fourier Transforms
- Polynomial Approximation
- Infinite Impulse Response Filters
- Finite Impulse Response Filters
- Image Processing Filters
Related Articles
New Articles
- Quantum Readiness Considerations for Suppliers and Manufacturers
- A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
- Early Interactive Short Isolation for Faster SoC Verification
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)
- Layout versus Schematic (LVS) Debug
- Usage of Multibit Flip-Flop and its Challenges in ASIC Physical Design
E-mail This Article | Printer-Friendly Page |