English
Versatile FPGA IP Handing, Creation, and Packaging
Joe Mallet, Synopsys
7/21/2016 02:00 PM EDT
The IEEE has ratified the 1735-2014 IEEE Recommended Practice for Encryption and Management of Electronic Design Intellectual Property (IP) specification.
Many companies are under pressure to deliver products to market faster so as to achieve the longest time in the market. This has led companies designing complex FPGAs to move increasingly toward licensing IP cores for the majority of the building blocks forming their designs, as opposed to creating their own custom versions in-house. The increased use of third-party IP to help accelerate schedules is creating challenges for FPGA designers as they now find themselves needing an automated methodology for handling various IP flows.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Synopsys, Inc. Hot IP
Related Articles
- High Quality IP creation through Efficient Packaging and Multiple Configuration Testing
- How FPGA packaging drives signal integrity
- Advanced Packaging and Chiplets Can Be for Everyone
- Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs
- The Role of Interconnection in the Evolution of Advanced Packaging Technology
New Articles
- Accelerating RISC-V development with Tessent UltraSight-V
- Automotive Ethernet Security Using MACsec
- What is JESD204C? A quick glance at the standard
- Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
- Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
Most Popular
- Accelerating RISC-V development with Tessent UltraSight-V
- System Verilog Assertions Simplified
- Synthesis Methodology & Netlist Qualification
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)